The present invention generally relates to an integrated circuit (IC) test, and more particularly, to a method and device of constructing a scan chain for a memory sequential test.
During design and production of an IC, a plurality of tests needs to be performed on the IC to ensure correctness of the product. For an IC containing a memory, generally at least the following three types of tests need to be performed thereon, including a logic test, a memory built-in test and a memory interface test.